The present invention relates to a semiconductor device, and more particularly, to a capacitor with a pillar type storage node and a method for fabricating the same.
Due to recent rapid development of ultra-fine semiconductor fabrication processes, the integration density of memory devices is rapidly increasing. Thus, a unit cell area is greatly reduced and a memory device operates at a lower voltage. However, in spite of the reduced unit cell area, charge capacity required for operation of a memory device must maintain an adequate capacity of more than 25 fF/cell in order to prevent soft error and reduction of a refresh time.
Under these circumstances, many research and development projects have been conducted on a metal-insulator-metal (MIM) capacitor employing a high-k dielectric layer in order to obtain sufficient charge capacity for next-generation dynamic random access memory (DRAM) devices.
In DRAM devices employing a 50 nm to 60 nm metal interconnection process, a storage node changes from a concave shape to a cylindrical shape in order to obtain more capacitance (that is, a cell capacitance of more than approximately 25 fF/cell).
However, the cylindrical storage node is difficult to use in a capacitor of a gigabit DRAM device employing the metal interconnection having sub-50-nm line width. This is because the cell region does not have enough space to form a capacitor by forming a dielectric layer of approximately 100 Å and a plate node of approximately 200 Å, while securing a space of approximately 25 nm (250 Å) for insulation between adjacent storage nodes.
Recently, there was proposed a capacitor with a pillar type storage node, which is capable of securing a sufficient space for insulation between adjacent storage nodes and obtaining high capacitance in sub-50-nm DRAM devices.
FIGS. 1A and 1B illustrate a method for fabricating a capacitor with a typical pillar type storage node.
Referring to FIG. 1A, a sacrificial layer 12 is formed over a substrate 11 where a predetermined process is completed. The sacrificial layer 12 is etched to form an open region, and a conductive layer 13 is formed to fill the open region.
Referring to FIG. 1B, a storage node 13A is formed by performing a storage node separating process on the conductive layer 13, a wet full dip out process is performed to remove the sacrificial layer 12.
However, a minute crevice 14 is formed over the center axis of the pillar type storage node 13A even if the conductive layer 13 is formed to fill the open region. Accordingly, a wet etchant can penetrate deeply into the minute crevice 14 during a subsequent wet full dip out process, and a part of the wet etchant can remain even after a drying process to cause a defect 15 such as watermarks.
Additionally, since the minute crevice 14 causes a shear stress between storage node walls on both sides of the minute crevice 14 during a subsequent thermal treatment, the storage node itself can bend to cause a bridge 16 between the adjacent storage nodes.